[Back]


Diploma and Master Theses (authored and supervised):

M. Fletzer:
"SPEAR2 - An Improved Version of SPEAR";
Supervisor: M. Delvai; Institut f. Technische Informatik, Embedded Computing Systems Group, 2008.



English abstract:
A soft core processor is a configureable microcontroller defined in software.
Such processors may be appropriate for a simple system, where the only
functionalities are the manipulation of general purpose I/O. Moreover, they
may also fit a complex system, where an operating system and interfaces like
Ethernet or DDR SDRAM are required.
In course of this master thesis, the soft core processor SPEAR2 has been
developed. The SPEAR2 architecture is a 16/32-bit processor and based on
SPEAR (Scalable Processor for Embedded Applications in Real-time Envi-
ronments).
The motives for developing an improved version are versatile. Fitting the
code to new target technologies, eliminating some disadvantages of SPEAR,
enabling configurability, or just adding useful features like byte addressed
memory.
To satisfy this goals, SPEAR2 was written from scratch. To provide ad-
justable memory sizes and the option to change the size of the data path, a
configuration framework has been created. Basically SPEAR2 is a 16-bit ar-
chitecture, but the data path can be extended to 32 bit. Considerable effort
had to be done to enable the correct interaction of two different data path
sizes with other components of the processor. The chief difficulty was mem-
ory access and developing a consistent bus interface. For both configurations
the same instruction set is used, enabling to use the same toolchain for both
configurations.
SPEAR2 was developed with the aim to be an efficient 16-bit processor. If
required, more computational power can be provided by extending the data
path. The gained experience showed, a 16-bit processor with extended data
path is not able to provide the performance of 32-bit processors, because of
the limited instruction set. Without extended data path SPEAR2 acts as
small and efficient processor, already used by some projects. The experience
shows, that the 16-bit configuration is able to compete with other soft core
processors.


Electronic version of the publication:
http://publik.tuwien.ac.at/files/PubDat_170329.pdf


Created from the Publication Database of the Vienna University of Technology.