Talks and Poster Presentations (with Proceedings-Entry):
W. Friesenbichler, T. Panhofer, M. Delvai:
"Improving Fault Tolerance by Using Reconﬁgurable Asynchronous Circuits";
Talk: 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2008,
- 2008-04-18; in: "Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on",
To achieve fault tolerance several tasks have to ϕ1
be performed, from fault detection up to recovery procedures.
Sophisticated methods for each sub-task were and are still
developed, but rarely a complete solution is proposed on circuit
level. This paper ﬁlls the gap by proposing a concept that
combines all required steps to implement fault tolerant digital
circuits. The approach is based on asynchronous Four-State
Logic (FSL) logic, which belongs to the family of Quasi Delay
Insensitive (QDI) circuits. Contrary to conventional approaches,
using synchronous logic plus additional hardware and/or software
to achieve fault tolerance, we use the inherent properties of FSL
for fault detection, fault localization and fault recovery. Only
deadlock detection and error mitigation require an enhancement
of the conventional FSL design. For this purpose, a monitoring
unit has to be added and self-healing cells were developed that
can be handled as conventional logic within the design ﬂow.
The feasibility of the approach is veriﬁed by a ﬁrst prototype
implementation of a fault tolerant adder circuit.
"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)
Created from the Publication Database of the Vienna University of Technology.