Contributions to Books:
"Time-Predictable Computer Architecture";
in: "EURASIP Journal on Embedded Systems",
issued by: HIndawi;
Today's general-purpose processors are optimized
for maximum throughput. Real-time systems need a processor
with both a reasonable and a known worst-case execution time
(WCET). Features such as pipelines with instruction dependencies,
caches, branch prediction, and out-of-order execution complicate
WCET analysis and lead to very conservative estimates.
In this paper, we evaluate the issues of current architectures with
respect to WCET analysis. Then, we propose solutions for a time-predictable
computer architecture. The proposed architecture
is evaluated with implementation of some features in a Java
processor. The resulting processor is a good target for WCET
analysis and still performs well in the average case.
"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)
Created from the Publication Database of the Vienna University of Technology.