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M. Ferringer:
"Coupling Asynchronous Signals into Asynchronous Logic";
Poster: Austrochip, Graz, Austria; 2009-09-07 - 2009-09-08; in: "Austrochip", Institut für Elektronik - TU Graz, (2009), ISBN: 978-3-9501635-1-3; 97 - 102.

In this paper we will discuss methodologies of interfacing delay-insensitive phased logic circuits. As for ordinary synchronous designs, special measures need to be taken into account when dealing with external asynchronous signals. In the case of phased logic, external (single-rail) signals must be converted into a dualrail representation, thereby not violating the internal registers´ timing constraints, and at the same time maintaining delay-insensitivity. In this paper we will provide an overview to different kinds of interfaces between synchronous and asynchronous designs and develop a conversion circuit that is suitable for phased logic designs, because it maintains delay-insensitivity at the internal interface.

Asynchronous, Synchronous, Coupling, VLSI

Project Head Andreas Steininger:
Asynchrone Logik in Echtzeitsystemen