Talks and Poster Presentations (with Proceedings-Entry):

R. Kirner, A. Kadlec, P. Puschner:
"Precise Worst-Case Execution Time Analysis for Processors with Timing Anomalies";
Talk: Euromicro Conference on Real-Time Systems (ECRTS), Dublin, Ireland; 2009-07-01 - 2009-07-03; in: "Proceedings of The 21th Euromicro Conference on Real-Time Systems", IEEE computer society, CPS, (2009), ISBN: 978-0-7695-3724-5; 119 - 128.

English abstract:
This paper explores timing anomalies in WCET analysis.
Timing anomalies add to the complexity of WCET
analysis and make it hard to apply divide-and-conquer
strategies to simplify the WCET assessment.
So far, timing anomalies have been described as a
problem that occurs when the WCET of a control-flow
graph is computed from the WCETs of its subgraphs, i.e.,
from a series decomposition. This paper extends the state
of the art by (i) showing that timing anomalies can as well
occur in a parallel decomposition of the WCET problem,
i.e., when complexity is reduced by splitting the hardware
state space and performing a separate WCET analysis for
hardware components that work in parallel, (ii) proving
that the potential occurrence of parallel timing anomalies
makes the parallel decomposition technique unsafe (i.e.,
one cannot guarantee that the calculated WCET bound
does not underestimate the WCET), and (iii) identifying
special cases of parallel timing anomalies for which the
parallel decomposition technique is safe. The latter provides
an important hint to hardware designers on their
way to constructing predictable hardware components.

"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)

Created from the Publication Database of the Vienna University of Technology.