Talks and Poster Presentations (with Proceedings-Entry):
M. Schoeberl, P. Puschner:
"Is Chip-Multiprocessing the End of Real-Time Scheduling?";
Talk: 9th International Workshop on Worst-Case Execution Time (WECT) Analysis,
2009-06-30; in: "Worst-Case Execution Time (WCET) Analsysis",
Austrian Computer Society,
Chip-multiprocessing is considered the future path for performance enhancements in computer architecture.
Eight processor cores on a single chip are state-of-the art and several hundreds of cores on
a single die are expected in the near future. General purpose computing is facing the challenge how
to use the many cores. However, in embedded real-time systems thread-level parallelism is naturally
used. In this paper we assume a system where we can dedicate a single core for each thread. In
that case classic real-time scheduling disappears. However, the threads, running on their dedicated
core, still compete for a shared resource, the main memory. A time-sliced memory arbiter is used to
avoid timing influences between threads. The schedule of the arbiter is integrated into the worst-case
execution time (WCET) analysis. The WCET results are used as a feedback to regenerate the arbiter
schedule. Therefore, we schedule memory access instead of CPU time.
Created from the Publication Database of the Vienna University of Technology.