Talks and Poster Presentations (with Proceedings-Entry):
M Függer, G. Fuchs, A. Steininger:
"On the Stability and Robustness of Non-Synchronous Circuits with Timing Loops";
Talk: WSDN 2009 (Workshop on Dependable and Secure Nanocomputing,
Estoril, Lisbon, Portugal;
- 2009-06-30; in: "WSDN 2009",
he tremendous advances in terms of speed and power consumption of nano-electronics devices come at a price, which considerably slows down further miniaturization. Among the most pressing issues are large parameter variations, primarily caused by process technology imperfections, that result in excessive delay variations, and continuously increasing soft error rates. The former seriously challenges the classic synchronous design paradigm, and coping with the latter requires suitable fault-tolerant architectures. Non-synchronous solutions, where the activity of one component is triggered by one or more other components explicitly, are hence gaining importance in future-generation deep submicron VLSI circuits. In this paper, we present first results of the parameter sensitivity analysis of our DARTS fault-tolerant clock generation scheme. Unlike conventional clocking techniques for GALS systems, DARTS does not use quartz oscillators, but generates approximately synchronized clocks by means of an asynchronous distributed algorithm. Both measurement and simulation results indicated deterministic fluctuations of the DARTS clock frequency, which depend strongly on the delay parameters, but could not be explained by noise or dynamic parameter variations. Non-linear control theory, applied to the non-fault-tolerant version of DARTS, eventually allowed us to develop an explanation of these effects, and established that any non-trivial closed-loop asynchronous circuit exhibits such deterministic timing variations. Additional simulation results confirmed that majority voting, as employed in the fault-tolerant version of DARTS, improves the robustness against parameter variations, but also considerably increases the complexity of the underlying control theory problem.
Non Synchornous Circuits, Timing Loops, Stability, Robustness
Project Head Andreas Steininger:
Verteilte Algorithmen für robuste Takt-Synchronisation
Created from the Publication Database of the Vienna University of Technology.