Vorträge und Posterpräsentationen (mit Tagungsband-Eintrag):
W. Friesenbichler, A. Steininger:
"Soft Error Tolerant Asynchronous Circuits based on Dual Redundant Four State Logic";
Vortrag: DSD 2009 (Euromicro Conference on Digital System Design),
Patras, Greece;
27.08.2009
- 29.08.2009; in: "12th EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - Architectures, Methods and Tools - DSD 2009",
IEEE Computer Society,
(2009),
ISBN: 9780769537825;
S. 100
- 107.
Kurzfassung englisch:
The continuing downscaling of integrated circuits makes modern devices more susceptible to soft errors. This paper investigates the possibility of using Four-State Logic (FSL) to improve the fault tolerance of digital circuits. FSL is a possible implementation of asynchronous Quasi Delay Insensitive (QDI) logic using a more efficient encoding and handshake protocol. The behavior of asynchronous circuits designed with FSL when subjected to transient faults is analyzed. We present methods based on dual redundancy that allow to detect as well as correct soft errors autonomously. The concept is demonstrated by fault injection experiments.
Schlagworte:
Asynchronous Logic, Four-State Logic, Sofr Error, Dual Redundancy, Fault Tolerance
"Offizielle" elektronische Version der Publikation (entsprechend ihrem Digital Object Identifier - DOI)
http://dx.doi.org/10.1109/DSD.2009.142
Erstellt aus der Publikationsdatenbank der Technischen Universität Wien.