[Back]

Talks and Poster Presentations (with Proceedings-Entry):

B. Charron-Bost, S. Dolev, J. Ebergen, U. Schmid:
"Fault Tolerant Distribiuted Algorithms and VLSI - An Appetizer";
Talk: Dagstuhl Seminar 08371 : Fault-Tolerant Distributed Algorithms on VLSI Chips, Dagstuhl, Germany (invited); 2009-09-07 - 2009-09-10; in: "Fault-Tolerant Distributed Algorithms on VLSI Chips", Leibniz Zentrum Informatik, 08371 (2009), ISSN: 1862-4405; ?.

English abstract:
From September the $7^{\text{th}}$, 2008 to September the $10^{\text{th}}$, 2008 the Dagstuhl Seminar 08371 Fault-Tolerant Distributed Algorithms on VLSI Chips " was held in Schloss Dagstuhl~--~Leibniz Center for Informatics. The seminar was devoted to exploring whether the wealth of existing fault-tolerant distributed algorithms research can be utilized for meeting the challenges of future-generation VLSI chips. During the seminar, several participants from both the VLSI and distributed algorithms' discipline, presented their current research, and ongoing work and possibilities for collaboration were discussed. Abstracts of the presentations given during the seminar as well as abstracts of seminar results and ideas are put together in this paper. The first section describes the seminar topics and goals in general. Links to extended abstracts or full papers are provided, if available.

Keywords:
Fault-tolerant distributed algorithms, fault tolerance, VLSI systems-on-chip, synchronous vs.\ asynchronous circuits, digital logic, specifications

Created from the Publication Database of the Vienna University of Technology.