[Zurück]

S. Edwards, S. Kim, E. Lee, I. Liu, H. Patel, M. Schoeberl:
"A Disruptive Computer Design Idea: Architectures with Repeatable Timing";
Vortrag: 2009 IEEE International Conference on Computer Design, Resort at Squaw Creek, Lake Tahoe, California; 04.10.2009 - 07.10.2009; in: "2009 IEEE International Conference on Computer Design", IEEE, CFP09ICD (2009), ISBN: 978-1-4244-5028-2; S. 54 - 59.

^This paper argues that repeatable timing is more
important and more achievable than predictable timing. It describes
microarchitecture approaches to pipelining and memory
hierarchy that deliver repeatable timing and promise comparable
or better performance compared to established techniques.
Specifically, threads are interleaved in a pipeline to eliminate
pipeline hazards, and a hierarchical memory architecture is
outlined that hides memory latencies.