Vorträge und Posterpräsentationen (mit Tagungsband-Eintrag):
G. Fuchs:
"Implications of VLSI Fault Models and Distributed Systems Failure Models --- A Hardware Designer's View";
Vortrag: Dagstuhl Seminar 08371 : Fault-Tolerant Distributed Algorithms on VLSI Chips,
Dagstuhl, Germany;
07.09.2009
- 10.09.2009; in: "Fault-Tolerant Distributed Algorithms on VLSI Chips",
Leibniz Zentrum Informatik,
08371
(2009),
ISSN: 1862-4405;
S. ?.
Kurzfassung englisch:
The fault and failure models as well as their semantics within the VLSI community and the distributed systems/algorithms community are quite different. Pointing out the mismatch of those fault respectively failure models is the main part of this work. The impact of the failure model in terms of hardware implementation effort and system complexity will be shown for different VLSI implementations of distributed algorithms. However, still, there are a lot of open questions left, mostly related to the coverage analysis of hardware implemented fault-tolerant algorithms.
Schlagworte:
VLSI, fault models, distribiuted systems, failure models
Zugeordnete Projekte:
Projektleitung Andreas Steininger:
Verteilte Algorithmen für robuste Takt-Synchronisation
Erstellt aus der Publikationsdatenbank der Technischen Universität Wien.