Talks and Poster Presentations (with Proceedings-Entry):
A. Wasicek, H. Kopetz, C. El Salloum:
"A System-on-a-Chip Platform for Mixed-Criticality Applications";
Talk: Proceedings of 13th IEEE International Symposium on Object/component/service-oriented Real-time distributed computing (ISORC'10),
Carmona, Seville, Spain;
- 2010-05-06; in: "Proceedings of 13th IEEE International Symposium on Object/component/service-oriented Real-time distributed computing (ISORC'10)",
High-integrity systems are deployed in order to realize safety-critical applications. To meet the rigorous requirements in this domain, these systems require a sophisticated approach to design, verification, and certification. Not only safety consideration shave an impact on a product's overall dependability, but also security has to be taken into account. In this paper we analyze the Time-Triggered System-on-Chip (TTSoC) architecture, which is a novel architecture for Multi-Processor System-on-Chip (MPSoC) devices, regarding its security properties. We discuss essential compliance criteria to the Multiple Independent Layers of Security (MILS) architecture, which is a industry-ready architecture for embedded high-integrity systems. We found that both architectures share intrinsic properties and we are able to show that the TTSoC architecture implements the core requirements of a MILS Separation Kernel and thus realizes its elementary security policies by design.
MILS , Mixed-criticality systems , TTSoC , multi?level security architecture
"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)
Created from the Publication Database of the Vienna University of Technology.