Talks and Poster Presentations (with Proceedings-Entry):
B. Cilku, P. Puschner:
"Towards a Time-Predictable Hierarchical Memory Architecture - Prefetching Options to be Explored";
Talk: Proc. 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops (ISORCW 2010),
Carmona, Sevilla, Spain;
- 2010-05-07; in: "Towards a Time-Predictable Hierarchical Memory Architecture - Prefetching Options to be Explored",
In this paper we explore a hierarchical memory architecture that simplifies the WCET prediction of tasks. Instead of using cache memories for speeding up code execution, we propose to use hierarchical memories that are similar to scratchpad memories. These memories are filled by explicit prefetch operations that are executed in synchrony with program execution. The instructions respectively the data that determine both the content and the timing of the operations that perform the memory transfers between the different memory levels are computed at code-generation time. The paper describes the overall system and memory architecture, and design choices for explicitly controlled time-predictable hierarchical memory architectures.
"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)
Created from the Publication Database of the Vienna University of Technology.