Vorträge und Posterpräsentationen (mit Tagungsband-Eintrag):
M. Jeitler, J. Lechner, A. Steininger:
"Enhancing Pipelined Processor Architectures with Fast Autonomous Recovery of Transient Faults";
Poster: DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems),
Vienna, Austria;
14.04.2010
- 16.04.2010; in: "13th IEEE International Symposium On Design And Diagnostics Of Electronic Cicruits And Systems",
IEEE Computer Society,
(2010),
ISBN: 9781424466108;
S. 233
- 236.
Kurzfassung englisch:
Recent technology trends have made radiationinduced soft errors a growing threat to the reliability of microprocessors, a problem previously only known to the aerospace industry. Therefore, the ability to handle higher soft error rates in modern processor architectures is essential in order to allow further technology scaling. This paper presents an efficient fault-tolerance method for pipeline-based processors using temporal redundancy. Instructions are executed twice at each pipeline stage, which allows the detection of transient faults. Once a fault is detected the execution is stopped immediately and recovery is implicitly performed within the pipeline stages. Due to this fast reaction the fault is contained at its origin and no expensive rollback operation is required later on.
"Offizielle" elektronische Version der Publikation (entsprechend ihrem Digital Object Identifier - DOI)
http://dx.doi.org/10.1109/DDECS.2010.5491776
Erstellt aus der Publikationsdatenbank der Technischen Universität Wien.