Talks and Poster Presentations (with Proceedings-Entry):

M. Jeitler, J. Lechner, A. Steininger:
"Enhancing Pipelined Processor Architectures with Fast Autonomous Recovery of Transient Faults";
Poster: DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria; 2010-04-14 - 2010-04-16; in: "13th IEEE International Symposium On Design And Diagnostics Of Electronic Cicruits And Systems", IEEE Computer Society, (2010), ISBN: 9781424466108; 233 - 236.

English abstract:
Recent technology trends have made radiationinduced soft errors a growing threat to the reliability of microprocessors, a problem previously only known to the aerospace industry. Therefore, the ability to handle higher soft error rates in modern processor architectures is essential in order to allow further technology scaling. This paper presents an efficient fault-tolerance method for pipeline-based processors using temporal redundancy. Instructions are executed twice at each pipeline stage, which allows the detection of transient faults. Once a fault is detected the execution is stopped immediately and recovery is implicitly performed within the pipeline stages. Due to this fast reaction the fault is contained at its origin and no expensive rollback operation is required later on.

"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)

Created from the Publication Database of the Vienna University of Technology.