Talks and Poster Presentations (without Proceedings-Entry):

G. Barany:
"Register Reuse Scheduling";
Talk: Gastvortrag ENS Lyon, Lyon (invited); 2011-04-08.

English abstract:
The amount of spill code generated by a compiler backend has crucial effects on program performance. Instruction scheduling before register allocation may cause live range overlaps that lead to suboptimal spill code. Even when a local scheduler tries to minimize register usage, its results can leave room for improvement regarding overall spill costs.

We present Register Reuse Scheduling (RRS), a novel approach to global register allocation that derives a register assignment while minimizing spill code by locally (re-)ordering independent operations. Using basic block data dependence graphs (DDGs), we identify possibly interfering live ranges whose interferences may be avoided by appropriate scheduling of instructions: Sequencing of independent computations allows the reuse of registers to avoid spilling. Such scheduling decisions may be enforced by adding arcs to the DDG. We use global spill cost information to identify a set of profitable arcs that enable register reuse. The corresponding interferences need not be present in the register allocation problem. A standard near-optimal register allocator computes a register assignment. The register reuses that are implicit in the assignment allow us to select arcs to add to the DDG and construct a schedule with minimal spill costs.

We present experimental data that shows that our approach can significantly decrease the amount of spills as compared to a local scheduling heuristic aimed at minimizing register usage. On average, we spill 8.9% fewer values and reduce static spill costs by 3.4%.

Electronic version of the publication:

Created from the Publication Database of the Vienna University of Technology.