Talks and Poster Presentations (with Proceedings-Entry):
M. Schoeberl, P. Schleuniger, W. Puffitsch, F. Brandner et al.:
"Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach";
Talk: First Workshop on Bringing Theory to Practice: Predictability and Performance in Embedded Systems (PPES 2011),
2011-03-16; in: "First Workshop on Bringing Theory to Practice: Predictability and Performance in Embedded Systems (PPES 2011)",
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case performance are hard to be modeled for the WCET analysis. In this paper we present Patmos, a processor optimized for low WCET bounds rather than high average case performance. Patmos is a dual-issue, statically scheduled RISC processor. The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average case performance.
Created from the Publication Database of the Vienna University of Technology.