Vorträge und Posterpräsentationen (mit Tagungsband-Eintrag):
V. Pavlu, A. Krall:
"Fast JIT Code Generation for x86-64 with LLVM";
Poster: ACACES 2011,
Fiuggi, Italien;
10.07.2010
- 16.07.2010; in: "ACACES 2011 Poster Abstracts",
HiPEAC,
7, Fiuggi, Italy
(2010),
ISBN: 9789038216317;
S. 289
- 290.
Kurzfassung englisch:
Our work focuses on investigating novel ways of efficient processor simulation using just-in-time compilation techniques. We can automatically generate a cycle-accurate simulator from a processor description that captures hardware structure and instruction set. The simulator employs an adaptive two-level just-in-time compilation scheme based on LLVM to attain high simulation speeds.
As the main source of slowdown during simulation we identified the LLVM code generator. We reduced compilation time in our own experimental code generator by an order of magnitude compared to LLVM´s original backend. Current work aims at leveraging instruction descriptions already available in LLVM to extend the coverage of our fast JIT code generator.
Schlagworte:
code generation; instruction selection; just-in-time compilation; simulation
Elektronische Version der Publikation:
http://publik.tuwien.ac.at/files/PubDat_203409.pdf
Zugeordnete Projekte:
Projektleitung Andreas Krall:
Optimale Code Erzeugung für explizit parallele Prozessoren
Erstellt aus der Publikationsdatenbank der Technischen Universität Wien.