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Talks and Poster Presentations (with Proceedings-Entry):

V. Pavlu, A. Krall:
"Fast JIT Code Generation for x86-64 with LLVM";
Poster: ACACES 2011, Fiuggi, Italien; 2010-07-10 - 2010-07-16; in: "ACACES 2011 Poster Abstracts", HiPEAC, 7, Fiuggi, Italy (2010), ISBN: 9789038216317; 289 - 290.



English abstract:
Our work focuses on investigating novel ways of efficient processor simulation using just-in-time compilation techniques. We can automatically generate a cycle-accurate simulator from a processor description that captures hardware structure and instruction set. The simulator employs an adaptive two-level just-in-time compilation scheme based on LLVM to attain high simulation speeds.
As the main source of slowdown during simulation we identified the LLVM code generator. We reduced compilation time in our own experimental code generator by an order of magnitude compared to LLVMs original backend. Current work aims at leveraging instruction descriptions already available in LLVM to extend the coverage of our fast JIT code generator.

Keywords:
code generation; instruction selection; just-in-time compilation; simulation


Electronic version of the publication:
http://publik.tuwien.ac.at/files/PubDat_203409.pdf



Related Projects:
Project Head Andreas Krall:
Optimale Code Erzeugung fr explizit parallele Prozessoren


Created from the Publication Database of the Vienna University of Technology.