Talks and Poster Presentations (without Proceedings-Entry):
"Optimal Code Generation for Explicitly Parallel Processors";
Talk: ETH Informatics Seminar,
In this talk ongoing work from a research project with the talk title is
presented. The aim of this project is to develop techniques for optimal and
heuristic integrated code generation for explicitly parallel processors (EPIC).
First results on register reuse scheduling are presented where spilling of
registers during register allocation is minimized by a local reordering of
independent operations. On average 8.9% less values are spilled resulting in
3.4% reduction of static spill cost. Other ongoing work on scheduling for
clustered architectures is discussed.
Created from the Publication Database of the Vienna University of Technology.