Talks and Poster Presentations (with Proceedings-Entry):

J. Lechner, R. Najvirt:
"A Generic Architecture for Robust Asynchronous Communication Links";
Poster: International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2012, Newcastle upon Tyne; 2012-09-04 - 2012-09-06; in: "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation", Lecture Notes in Computer Science, 7606 (2013), ISBN: 978-3-642-36156-2; 121 - 130.

English abstract:
This paper proposes a new generic architecture for building robust communication links for globally asynchronous locally synchronous (GALS) circuits. The general idea is to use delay-insensitive codes along with error detecting codes to provide resilience against transient faults as well as robustness against delay variations. The presented link architecture is completely generic with respect to the chosen handshake protocols (2-phase/4-phase) and the used codes. Thus a specific implementation can be individually optimized regarding features such as performance, power consumption, area complexity or the number of faults that can be tolerated. In order to demonstrate the flexibility of our approach we present several solutions based on 2-phase and 4-phase dual-rail codes combined with either single parity bits or Hamming codes for error detection. In the former case the link provides resilience against single faults, in the latter double faults can be mitigated.

Created from the Publication Database of the Vienna University of Technology.