Talks and Poster Presentations (with Proceedings-Entry):
J. Lechner, M. Lampacher, T. Polzer:
"A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding";
Talk: 2012 International Conference on Application of Concurrency to System Design (ACSD 2012),
- 2012-06-29; in: "Application of Concurrency to System Design (ACSD), 2012 12th International Conference on",
This paper proposes new robust asynchronous interfaces for GALS-systems. A combination of delay-insensitive and error detecting/correcting codes is used to achieve two types of robustness: variation-tolerance and fault-tolerance. Concerning the delay-insensitive code this paper targets the well-known 4-phase dual rail code, frequently used in asynchronous circuit design. In order to enable an optimal choice of the used error detecting/correcting code, a precise fault model and a general classiﬁcation of possible interconnect architectures is presented. The goal is to tolerate single-bit errors with maximum coding efﬁciency, i.e., with minimal overheads for interconnect resources. This is accomplished by fully utilizing the information redundancy provided by the combination of the delay-insensitive code and an appropriate error detecting/correcting code. Metastable upsets, however, cannot be handled with error correcting codes alone. Faults can occur at arbitrary times and thus compromise system timing. Even though metastability cannot be avoided, a metastability-tolerant implementation is presented, which waits for a metastable upset to resolve before processing a new data word. This guarantees correct data transmission regardless of the timing of erroneous inputs.
Created from the Publication Database of the Vienna University of Technology.