Vorträge und Posterpräsentationen (mit Tagungsband-Eintrag):
M. Wimmer, M. Pöter, J. Träff:
"The Pheet Task-Scheduling Framework on the Intel(R) Xeon Phi(TM)Coprocessor and other Multicore Architectures";
Vortrag: Workshop on Multithreaded Architectures and Applications (MTAAP 2013) in conjunction with IPDPS 2013,
Boston, Massachusetts, USA;
- 24.05.2013; in: "Proceedings of the 2013 IEEE 27th International Symposium on Parallel and Distributed Processing Workshops and PhD Forum",
IEEE Computer Society,
Pheet, a task-scheduling framework that allows for easy customization of internal data-structures, is a research vehicle for experimenting with high-level application and low-level architectural support for task-parallel programming models. Pheet is highly configurable, and allows comparison between different implementations of data structures used in the scheduler, as well as comparisons between entirely different schedulers (typically using work-stealing). Pheet is being used to investigate high-level task-parallel support mechanisms that allow applications to influence scheduling decisions and behavior. One such mechanism, that we use in this work, is scheduling strategies. Previous Pheet benchmarking was done on conventional multicore architectures from AMD and Intel. In this paper we discuss the performance of Pheet on a prototype Intel Xeon Phi coprocessor with 61 cores. We compare these results to Pheet on three conventional multicore architectures. Using two benchmarks from the mostly non-numerical/combinatorial Pheet suite we find that the Xeon Phi coprocessor provides considerably better scalability than the other architectures, with more than a 70x speedup on the 61-core Knights Corner prototype system when using 4-way SMT, although not achieving the same absolute performance. For our research, the Xeon Phi coprocessor is an interesting architecture for implementing and evaluating fine-grained task-parallel parallel algorithm implementations.
Work-stealing, fine-grained multi threaded applications, strategies, priorities, Xeon Phi
"Offizielle" elektronische Version der Publikation (entsprechend ihrem Digital Object Identifier - DOI)
Projektleitung Jesper Larsson Träff:
Performance Portability and Programmability for Heterogeneous Many-core Architectures
Erstellt aus der Publikationsdatenbank der Technischen Universität Wien.