Talks and Poster Presentations (with Proceedings-Entry):

V. S. Veeravalli, A. Steininger:
"Performance of Radiation Hardening Techniques under Voltage and Temperature Variations";
Talk: 2013 IEEE Aerospace Conference, Big Sky, Montana, USA; 2013-03-02 - 2013-03-09; in: "Proc. 2013 IEEE Aerospace Conference", (2013), 6 pages.

English abstract:
The effectiveness of the techniques to mitigate radiation
particle hits in digital CMOS circuits has been mainly
studied under a given set of environmental conditions. This paper
will explicitly analyze, how the performance of two selected
radiation hardening techniques, namely transistor sizing and
stack separation, varies with temperature and supply voltage.
Our target is an inverter circuit in UMC90 bulk CMOS technology,
instances of which have been hardened against charges
of 300fC and 450fC using either of the two techniques under
investigation. In a Spice simulation we apply particle hits to
these circuits through double-exponential current pulses of the
respective charge. We study the effect of these pulses in a
temperature range from -55 C to +175 C and a supply voltage
of 0.65 to 1.2V (nominal 1V) at the output of a (unhardened)
buffer that has been connected as a load. For the hardening by
sizing we observe proper operation in the range from 1.2V to
900mV, while for lower supply we observe full swing pulses of
increasing magnitude when the respective maximum charge is
applied. The influence of temperature turns out to be minor.
For the stack separation approach the observation is similar,
however, the circuit starts glitching only at 750mV. Our study
allows the following conclusions: (i) The effectiveness of the
hardening approaches strongly depends on the supply voltage,
and moderately on temperature. (ii) As expected, low voltage
and high temperature represent the worst case for rad-hard
sizing. Stack separation, on the other hand, unexpectedly shows
a stronger and more complicated temperature dependence. (ii)
For voltages below approx. 90% of nominal the hardening
by sizing fails, when designed for nominal voltage and room
temperature. The approach can be enhanced to survive this
worst case by increasing the sizing factor further by more than
3 times. (iv) The stack separation only fails for voltages below
approx. 75% of nominal, but there is no simple remedy to make
it reliable for a larger range. This must be considered when
judging the appropriateness of this method for a given purpose.
Also it turned out that once it fails, the resulting SET pulse has
considerable length.

Created from the Publication Database of the Vienna University of Technology.