Talks and Poster Presentations (with Proceedings-Entry):
T. Polzer, A. Steininger:
"An Approach for Efficient Metastability Characterization of FPGAs through the Designer";
Talk: 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2013),
Santa Monica, CA;
- 2013-05-22; in: "19th IEEE International Symposium on Asynchronous Circuits and Systems",
The efficient design of a synchronizer for a given MTBF limit heavily depends on the availability of an accurate metastability characterization of the bistables in the target technology. We propose a measurement approach for FPGAs that comes along without any specific measurement infrastructure and can hence be performed by the designer with relatively low efforts, but is yet very accurate. Our concept comprises the use of the FPGA-internal digital clock manager (DCM), calibration measurements for the latter, averaging over several parallel measurement runs, and separated analysis of different metastability cases. To demonstrate the power of our approach we present detailed measurement results for a Xilinx Virtex-4 FPGA that even show slave metastability. Furthermore, we discuss how diverse constraints can be considered to make the measurement more accurate and time efficient.
Created from the Publication Database of the Vienna University of Technology.