H. Mahmoudi, T. Windbacher, V. Sverdlov, S. Selberherr:
"RRAM Implication Logic Gates";
Patent: Europe, Nr. EP 2 736 044 A1 ; eingereicht: 22.11.2012, erteilt: 28.05.2014.

Kurzfassung englisch:
The invention relates to an electronic circuit (200, 400) comprising a plurality of bit cells (210, 410) arranged in an array and being selectable by row lines (222, 422) and column lines (232, 432), at least one row driver (220, 420), at least one column driver (230, 430), and a readout circuit (260, 460), wherein each bit cell (210, 410) comprises an access transistor (214, 414) and a non-volatile resistive-switching element (212, 412) with at least two resistance states, wherein the row driver (220, 420) and the column driver (230, 430) are capable to simultaneously apply a selecting voltage V_s to a first row line (222, 422) to select a target bit cell (210, 410), a pre-selecting voltage V_p-s to a second row line (222', 422') to select a source bit cell (210' 410'), and a logic current I_imp to at least one column line (232, 432), wherein the selecting voltage V_s is higher than the pre-selecting voltage V_p-s.

Elektronische Version der Publikation:

Erstellt aus der Publikationsdatenbank der Technischen Universitšt Wien.