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V. S. Veeravalli, A. Steininger, U. Schmid:
"Measuring SET Pulsewidths in Logic Gates using Digital Infrastructure";
Vortrag: 15th International Symposium & Exhibit on Quality Electronic Design, Santa Clara, USA; 10.03.2014 - 12.03.2014; in: "Proceedings 15th International Symposium & Exhibit on Quality Electronic Design", (2014), ISBN: 978-1-4799-3946-6; 7 S.

We present a purely digital infrastructure for measuring SET pulsewidths in logic gates. Such a facility is crucial for experimentally studying radiation sensitivity and SET propagation of a circuit. Our digital-only implementation facilitates measurement within a standard cell CMOS chip, without the need of any analog or customized circuitry on-chip. Besides high resolution and area efficiency, a fundamental requirement guiding the development of our solution was radiation tolerance, as it shall be employed on a test chip that is fully exposed to radiation in an experimental study. We validate our architecture, for various primary radiation target circuits, by analog simulation, injecting SETs of varying strength using the standard double-exponential current model.

http://dx.doi.org/10.1109/ISQED.2014.6783331