Publications in Scientific Journals:
B. Rahbaran, A. Steininger:
"Is Asynchronous Logic More Robust Than Synchronous Logic?";
IEEE Transactions on Dependable and Secure Computing,
With clock rates beyond 1 GHz, the model of a systemwide synchronous clock is becoming difficult to maintain; therefore,
asynchronous design styles are increasingly receiving attention. While the traditional synchronous design style is well-proven and
backed up by a rich field experience, comparatively little is known about the properties of asynchronous circuits in practical application.
In the face of increased transient fault rates, robustness is a crucial property, and from a conceptual view, the so-called
"delay-insensitive" asynchronous design approaches promise to be more robust than synchronous ones, since their operation does not
depend on tight timing margins, and data are two-rail coded. A practical assessment of asynchronous designs in fault-injection (FI)
studies, however, can rarely be found, and there is a lack of adequate methods and tools in this particular domain. Therefore, the
objective of this work is 1) to provide a common approach for efficient and accurate FI in synchronous and in asynchronous designs,
and 2) to experimentally compare the robustness of both synchronous and asynchronous designs. To this end, a synchronous 16-bit
processor as well as its asynchronous (delay insensitive) equivalent are subjected to signal flips and delay faults. The results of over
489 million experiments are summarized and discussed, and a detailed discussion on the specific properties of the chosen
asynchronous design style is given.
"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)
Created from the Publication Database of the Vienna University of Technology.