Talks and Poster Presentations (with Proceedings-Entry):

B. Cilku, P. Puschner:
"Designing a Time-Predictable Memory Hierarchy for Single-Path Code";
Talk: 7 th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems (CRTS14), Rome, Italy; 2014-12-02; in: "Designing a Time-Predictable Memory Hierarchy for Single-Path Code", (2014), 9 - 14.

English abstract:
Trustable Worst-Case Execution-Time (WCET) bounds are
a necessary component for the construction and veri cation
of hard real-time computer systems. Deriving such bounds
for contemporary hardware/software systems is a complex
task. The single-path conversion overcomes this di culty
by transforming all unpredictable branch alternatives in the
code to a sequential code structure with a single execution
trace. However, the simpler code structure and analysis of
single-path code comes at the cost of a longer execution
time. In this paper we address the problem of the execu-
tion performance of single-path code. We propose a new
instuction-prefetch scheme and cache organization that uti-
lize the \knowledge of the future" properties of single-path
code to reduce the main memory access latency and the
number of cache misses, thus speeding up the execution of
single-path programs.

Electronic version of the publication:

Created from the Publication Database of the Vienna University of Technology.