Vorträge und Posterpräsentationen (mit Tagungsband-Eintrag):
V. S. Veeravalli, A. Steininger:
"Long Term On-Chip Monitoring of SET Pulsewidths in a Fully Digital ASIC";
Vortrag: 22nd Austrian Workshop on Microelectronics,
Graz;
09.10.2014; in: "Proceedings of the 22nd Austrian Workshop on Micorelectronics",
IEEE,
(2014),
ISBN: 978-1-4799-7243-2;
Paper-Nr. 24,
6 S.
Kurzfassung englisch:
We present the design of an all-digital
measurement circuit for the pulsewidth of single-event transients
(SETs). It is used as an on-chip infrastructure block on a target
chip that will be subjected to radiation in an experimental study.
Therefore it needs to be area-efficient, robust and fast at the
same time. A special feature of our proposed design is to allow
recording a vector of SET pulse widths, thus avoiding the need
for frequent read-out during the ongoing experiment. We prove
the proper operation of our circuit by means of SET injection in
a pre-layout simulation for a 90nm UMC bulk CMOS
implementation.
Schlagworte:
Single-event transient; on-chip infrastructure, pulse width measurement
"Offizielle" elektronische Version der Publikation (entsprechend ihrem Digital Object Identifier - DOI)
http://dx.doi.org/10.1109/Austrochip.2014.6946318
Zugeordnete Projekte:
Projektleitung Andreas Steininger:
Analysis & Modeling of Single-Event-Transients in VLSI Chips
Erstellt aus der Publikationsdatenbank der Technischen Universität Wien.