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A. Steininger, V. S. Veeravalli, D. Alexandrescu, E. Costenaro, L. Anghel:
"Exploring the State Dependent SET Sensitivity of Asynchronous Logic - The Muller-Pipeline Example";
Talk: 2014 32nd IEEE International Conference on Computer Design (ICCD), Seoul, Korea; 2014-10-19 - 2014-10-22; in: "Proceedings of the 2014 32nd IEEE International Conference on Computer Design (ICCD)", IEEE, (2014), ISBN: 978-1-4799-6492-5; Paper ID 69, 7 pages.

Asynchronous circuits exhibit considerable advantages
over their synchronous counterparts, like lower dynamic
power and inherent variation tolerance, which makes them
increasingly interesting. Their fault-tolerance behavior, however,
is not yet fully explored. In particular, temporal masking, as
seen with synchronous circuits, seems to be completely nonexistent
in asynchronous logic. Instead, there seem to be other
masking mechanisms in the control structure that establish an
extra barrier for transient fault propagation. In this paper
we will explore these masking mechanisms in a qualitative as
well as quantitative manner. To this end we first analyze the
behavior of a Muller C-element, one fundamental building block
in asynchronous designs. In a next step we evaluate the behavior
of a chain of these elements, forming a so-called Muller pipeline,
the basic control structure of many asynchronous designs, under
transient faults. To validate our theoretical findings we inject
radiation induced single event transients (SETs) in an extensive
simulation campaign. The results show that the SET susceptibility
of the Muller pipeline is indeed state dependent. This knowledge
can be leveraged to improve, e.g., the radiation hardness of
asynchronous circuits by preferring the more robust states in
their design wherever possible.

http://dx.doi.org/10.1109/ICCD.2014.6974663

Project Head Andreas Steininger:
Analysis & Modeling of Single-Event-Transients in VLSI Chips