Talks and Poster Presentations (with Proceedings-Entry):

R. Najvirt, A. Steininger:
"Equivalence of Clock Gating and Synchronization with Applicability to GALS Communication";
Talk: 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, Isles Balears, Spain; 2014-09-29 - 2014-10-01; in: "Proceedings of the 24th International Workshop on Power and Timing Modeling, Optimization and Simulation", IEEE, (2014), ISBN: 978-1-4799-5412-4; Paper ID 29, 8 pages.

English abstract:
Pausible clocking is a very popular approach for
clock domain interfacing in GALS systems. However, accuracy
and stability of the ring oscillator that is central to this principle
are bad. This suggests to use gated crystal oscillators instead. In
this paper we will formally show that the problem of clock gating
is equivalent to the synchronization problem. We will present a
fundamental block diagram for a gated clock, comprising an
AND gate and a synchronizer for the control input, and will
give evidence that the related circuits proposed so far in the
literature are instantiations of this principle. According to our
equivalence proof none of these circuits can hence be free from a
residual risk of metastability; typically the MTBF is determined
by the synchronizer block. This stands in contrast to the pausible
clocking where the arbiter can safely prevent metastable outputs.
We further argue that a handshake based data transfer (without
clock stopping) yields essentially the same properties wrt. MTBF
and performance, while causing more localized effects in case of
a metastable upset. In conclusion the use of clock gating does
not seem to provide any advantages over the alternative schemes
and can hence not be recommended.

"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)

Created from the Publication Database of the Vienna University of Technology.