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N. Kim, A. Krall:
"Integrated Modulo Scheduling and Cluster Assignment for TI TMS320C64x+ Architecture";
Talk: ODES-11: 11th Workshop on Optimizations for DSP and Embedded Systems, Orlando, USA; 02-15-2014; in: "ODES-11: 11th Workshop on Optimizations for DSP and Embedded Systems", (2014), 25 - 32.

For the exploitation of the available parallelism clustered Very Long Instruction Word (VLIW) processors rely on highly optimizing compilers. Aiming this parallelism, many advanced compiler concepts have been developed and proposed in the past. Many of them concentrate on loops only as most of the execution time is usually spent executing repeating patterns of code. Software pipelining techniques, such as modulo scheduling, try to speed up the execution of loops by simultaneous initiation of multiple iterations, thus additionally exploiting parallelism across loop iteration boundaries. This increases processor utilization at the cost of higher complexity which is especially true for architectures featuring multiple clusters and distributed register files. Additional scheduling constraints need to be considered in order to produce valid schedules. Targeting TI's TMS320C64x+ clustered VLIW architecture, we describe a code generation approach that adapts an iterative modulo scheduling scheme, and also propose two heuristics for cluster assignment, all together implemented within the popular LLVM compiler framework. We cover implementation of developed algorithms, present evaluation results for a selection of benchmarks popular for embedded system development and discuss gained insights on the topics of integrated modulo scheduling and cluster assignment in this paper.

VLIW, instruction level parallelism, modulo scheduling, cluster assignment, phase ordering, integer linear programming, LLVM

http://dx.doi.org/10.1145/2568326.2568327