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X. Chen, Z. Lu, A. Jantsch et al.:
"Achieving Memory Access Equalization via Round-trip Routing Latency Prediction in 3D Many-core NoCs";
Vortrag: IEEE Annual Symposium on VLSI (ISVLSI), Montpellier; 08.07.2015 - 10.07.2015; in: "Proceedings of IEEE Annual Symposium on VLSI (ISVLSI)", (2015), ISBN: 978-1-4799-8718-4; 6 S.

3D many-core NoCs are emerging architectures for
future high-performance single chips due to its integration of many
processor cores and memories by stacking multiple layers. In such
architecture, because processor cores and memories reside in dif-
ferent locations (center, corner, edge, etc.), memory accesses behave
differently due to their different communication distances, and the
performance (latency) gap of different memory accesses becomes
larger as the network size is scaled up. This phenomenon may lead
to very high latencies suffered from by some memory accesses, thus
degrading the system performance. To achieve high performance, it
is crucial to reduce the number of memory accesses with very high
latencies. However, this should be done with care since shortening
the latency of one memory access can worsen the latency of another
as a result of shared network resources. Therefore, the goal should
focus on narrowing the latency difference of memory accesses. In the
paper, we address the goal by proposing to prioritize the memory
access packets based on predicting the round-trip routing latencies of
memory accesses. The communication distance and the number of the
occupied items in the buffers in the remaining routing path are used
to predict the round-trip latency of a memory access. The predicted
round-trip routing latency is used as the base to arbitrate the memory
access packets so that the memory access with potential high latency
can be transferred as early and fast as possible, thus equalizing the
memory access latencies as much as possible. Experiments with varied
network sizes and packet injection rates prove that our approach can
achieve the goal of memory access equalization and outperforms the
classic round-robin arbitration in terms of maximum latency, average
latency, and LSD
1
. In the experiments, the maximum improvement
of the maximum latency, the average latency and the LSD are 80%,
14%, and 45% respectively.

http://dx.doi.org/10.1109/ISVLSI.2015.8