[Back]

J. Wang, M. Ebrahimi, L. Huang, A. Jantsch, G. Li:
"Design of Fault-Tolerant and Reliable Networks-on-Chip";
Talk: IEEE Annual Symposium on VLSI (ISVLSI), Montpellier; 2015-07-08 - 2015-07-10; in: "Proceedings of IEEE Annual Symposium on VLSI (ISVLSI)", (2015), ISBN: 978-1-4799-8718-4; Paper ID 545-550, 6 pages.

Networks-on-Chips (NoCs) are at the core of high
performance multi-processor systems-on-chips. As the number
of cores and sub-systems on chip grow, the size and complexity
of NoCs increase as well. Due to the process variation, aging
effects and soft-errors in current and expected future process
generations, the probability of failure in the NoCs rises and has
to be fought at all levels: circuit, architecture, and communication
protocols.
This paper discusses appropriate fault models for NoCs
and their effects on the architecture and network levels. A
method to design fault-tolerant NoCs comprising of techniques
at the link level, the routing level, and the end-to-end level
of the communication is presented. In addition, the proposed
method offers an isolation technique where the computing cores
are decoupled from the faults in the network. This technique
avoids or at least attenuates the severe impacts of faults on the
network performance and functionality. These point techniques
are combined together to design fault-tolerant and reliable NoCs

http://dx.doi.org/10.1109/ISVLSI.2015.33