Vorträge und Posterpräsentationen (mit Tagungsband-Eintrag):
R. Ma, Z. Hui, A. Jantsch:
"A Packet-switched Interconnect for Many-core Systems with {BE} and {RT} Service";
Vortrag: Design, Automation and Test in Europe (DATE),
Grenoble, France;
14.03.2015
- 18.03.2015; in: "Proceedings of the Design Automation and Test Europe Conference (DATE)",
(2015),
ISBN: 978-3-9815370-4-8;
4 S.
Kurzfassung englisch:
A packet-switched interconnect design which
supports real-time and best-effort services is proposed.
This interconnect is different from traditional NoCs in
that we use direction channels to replace the large input
buffers and use less resource to realize the network
transfer. The connection between our interconnect design
and IP core is an on-chip memory management block
named DME. The real-time service implies preferential
transfer channel allocation, maximum delay bound and
time stamping of every real-time packet. The solution is
geared towards many-core systems, such as complex
industrial control systems and communication devices,
which require these features to facilitate efficient SW and
application development.
Schlagworte:
NoC router; packet-switched; real-time; best-effort;
"Offizielle" elektronische Version der Publikation (entsprechend ihrem Digital Object Identifier - DOI)
http://dx.doi.org/10.7873/DATE.2015.0405
Erstellt aus der Publikationsdatenbank der Technischen Universität Wien.