Talks and Poster Presentations (with Proceedings-Entry):
Y. Zhang, L. Li, A. Jantsch, Z. Lu, M. Gao, Y. Fu, H. Pan:
"Exploring Stacked Main Memory Architecture for 3D GPGPUs";
Talk: IEEE International Conference on ASIC (ASICON),
Chengdu;
2015-11-03
- 2015-11-06; in: "IEEE International Conference on ASIC (ASICON)",
IEEE,
Chengdu
(2015),
Paper ID 646,
4 pages.
English abstract:
The tremendous number of threads on general purpose
graphic processing units (GPGPUs) poses significant
challenges on memory architecture design. 3D stacked
main memory architecture atop GPGPU is a potential
approach to provide high data communication bandwidth
and low access latency to meet the requirement of
GPGPUs. In this paper, we explore the performance of
3D GPGPUs with stacked main memory. The
experimental results show that the 3D stacked GPGPU
can provide up to 124.1% and on average 55.8%
performance improvement compared to a 2D GPGPU
scheme.
Created from the Publication Database of the Vienna University of Technology.