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R. Najvirt, T. Polzer, F. Beck, A. Steininger:
"Containment of Metastable Voltages in FPGAs";
Talk: 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Belgrad; 2015-04-22 - 2015-04-24; in: "18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", (2015), 6 pages.

The significant PVT variations seen with modern
technologies make synchronous design inefficient. Asynchronous
design with its flexible timing is a promising alternative, but
prototyping is difficult on the available FPGA platforms which
are clock centric and do not provide the required functional
primitives like mutual exclusion or Muller C-elements. The
solutions proposed in the literature work nicely in principle,
but cannot safely handle metastability issues that are inevitable
at interfaces even in asynchronous designs. In this paper we
propose a reliable implementation of a Schmitt-trigger, which
allows to safely convert potential intermediate voltage levels
that result from metastability into late transitions that can be
reliably handled in the asynchronous domain. Beyond the actual
circuit we also discuss the associated routing constraints to make
the circuit work properly in spite of the uncertain routing
within FPGAs. Furthermore we propose a procedure for an
"in situ reliability assessment" of the specific Schmitt-trigger
element under consideration, which also applies to metastability
containment with high- or low-threshold inverters only. Our proof
of concept is based on experimental results for both Xilinx and
Altera FPGA platforms.