Talks and Poster Presentations (with Proceedings-Entry):

R. Najvirt, A. Steininger:
"A Versatile and Reliable Glitch Filter for Clocks";
Talk: 25th International Workshop on Power and Timing Modeling, Optimization and Simulation, Salvador, Brasilien; 2015-09-01 - 2015-09-04; in: "25th International Workshop on Power and Timing Modeling, Optimization and Simulation", (2015), 8 pages.

English abstract:
In today´s complex system-on-chip architectures
the protection of the clock(s) against glitches introduced by
environmental disturbances, attackers, or gating measures is
becoming increasingly important. Glitch protection is a delicate
issue in the digital domain, as it is inherently coupled with
metastability issues. The circuit we propose in this paper outputs
a clock that strictly follows an input reference clock in the regular
case, but guarantees a minimum output pulse width even in case
of arbitrary behavior of the reference. We will give a thorough
analysis showing that, unlike most existing solutions, our circuit
can handle metastability without any residual risk of upsets. Still
its implementation is very simple. Our theoretical claims will be
supported by simulation results. Furthermore, we will give some
examples on possible use cases for such a circuit, like clock gating,
clock self-repair, or defense against clock attacks.

Created from the Publication Database of the Vienna University of Technology.