Talks and Poster Presentations (with Proceedings-Entry):

B. Cilku, D. Prokesch, P. Puschner:
"A Time-Predictable Instruction-Cache Architecture that Uses Prefetching and Cache Locking";
Talk: 11th International IEEE/IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems SEUS 2015, Auckland, New Zealand; 2015-04-13; in: "Proc. 18th IEEE International Symposium on Real-Time Computing (ISORC 2015) Workshops", IEEE, (2015), ISBN: 978-1-4673-7709-6; 74 - 79.

English abstract:
Trustable Worst-Case Execution-Time (WCET) bounds are a necessary component for the construction and verification of hard real-time computer systems. Deriving such bounds for contemporary hardware/software systems is a complex task. The single-path conversion overcomes this difficulty by transforming all unpredictable branch alternatives in the code to a sequential code structure with a single execution trace. However, the simpler code structure and analysis of single-path code comes at the cost of a longer execution time. In this paper we address the problem of the execution performance of single-path code. We present a new cache organization that utilizes the principle of locality of single-path code to reduce cache miss latency and cache miss rate. The proposed cache memory architecture combines cache prefetching and cache locking, so that the prefetcher capitalizes on spatial locality while the locker makes use of temporal locality. The demonstration section shows how these two techniques can complement each other.

predictability, cache, prefetching, locking, single-path code

"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)

Created from the Publication Database of the Vienna University of Technology.