Talks and Poster Presentations (with Proceedings-Entry):

T. Polzer, F. Huemer, A. Steininger:
"A Programmable Delay Line for Metastability Characterization in FPGAs";
Talk: 24th Austrian Workshop on Microelectronics (Austrochip), Villach; 2016-10-19; in: "Proceedings 24th Austrian Workshop on Microelectronics", (2016), 6 pages.

English abstract:
The experimental metastability characterization
of a flip flop requires a controllable delay with low jitter and
high time resolution. In FPGAs such an experiment can be
very useful for in-situ or even online characterization of a
given flip flop, but existing solutions rely on the availability of
a digital clock manager (DCM) or a phase locked loop (PLL)
for implementing this controllable delay. Given that such a
component may not always be available, and that its linearity
is sometimes sub-optimal and hard to calibrate, we present an
alternative approach in this paper. It is based on the use of
the carry chain for determining the delay steps, which allows a
very fine resolution. For calibration of the step sizes we propose
to operate the delay line in a ring oscillator whose frequency
is then measured for all delay settings. Our results show that
this solution yields a fine-grain delay control with acceptable
jitter. We demonstrate the usefulness of our approach in the
context of a complete metastability characterization that now
can be performed without requiring a DCM or PLL.

metastability, delay line, late transition detection, carry chain

Created from the Publication Database of the Vienna University of Technology.