Talks and Poster Presentations (with Proceedings-Entry):

V. S. Veeravalli, A. Steininger:
"Design and Physical Implementation of a Target ASIC for SET Experiments";
Poster: 2016 Euromicro Conference on Digital System Design (DSD), Limassol, Portugal; 2016-08-31 - 2016-09-02; in: "Proc. 2016 Euromicro Conference on Digital System Design (DSD)", IEEE, (2016), ISBN: 978-1-5090-2817-7; 694 - 697.

English abstract:
We present design aims and implementation results
of a digital ASIC that is dedicated as a target for radiation
experiments. Accordingly, it carries different target circuit blocks
whose purpose is to study susceptibility to radiation as well as
propagation of radiation effects. On-chip measurement infrastructure
is mainly comprised of counters that record singleevent
transients in various nodes of the target blocks. As it
competes with the target blocks for chip area, it must be kept
as small as possible, in spite of the need of being tolerant to
particle hits in itself, which cannot be avoided in some types of
radiation experiments. We sketch our respective solutions and
present the resulting area distribution of the final ASIC layout
for an industrial 65nm bulk CMOS process. We also show how
we optimized the layout for the purpose of our experiments and
present all relevant implementation details.

radiation experiments, asynchronous circuits, single-event transients

Related Projects:
Project Head Andreas Steininger:
Analysis & Modeling of Single-Event-Transients in VLSI Chips

Created from the Publication Database of the Vienna University of Technology.