Talks and Poster Presentations (with Proceedings-Entry):

T. Polzer, A. Steininger:
"A General Approach for Comparing Metastable Behavior of Digital CMOS Gates";
Talk: 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Kosice, Slovakia; 2016-04-20 - 2016-04-22; in: "Proc 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", (2016), ISBN: 978-1-5090-2467-4; 6 pages.

English abstract:
In digital CMOS essentially all sequential function
blocks may get metastable in one way or another, when
provided with marginal inputs. Most often the result is a
delayed reaction at the output, which, in a synchronous
design, potentially violates the timing assumptions. Therefore
metastable behavior is often characterized by the Mean Time
Between Upset (MTBU), which reflects the expected interval
between such violations on a statistical base.
However, not all designs are synchronous - there are even
sequential elements specifically intended for use in context
with elastic timing, such as the mutual exclusion element
or the Muller C-element. For these a characterization via
MTBU is not useful; but on the other hand there seem to
be no reasonable alternatives. Therefore in this paper we
propose the use of the delay graph (over the relevant quantity
that causes metastability when becoming marginal) for this
purpose. We elaborate its correspondence with the usual
MTBU graph and the metastability parameters, namely tau
and T0. As a proof of concept we apply our strategy to a
set of sequential elements, like D-latch, RS-latch, Muller Celement
and mutex and discuss the differences we identified.

Metastability, reliability model, mean time between failure

Created from the Publication Database of the Vienna University of Technology.