[Zurück]

A. Kinali, F. Huemer, C. Lenzen:
"Fault-tolerant Clock Synchronization with High Precision";
Vortrag: 2016 IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, PA, USA; 11.07.2016 - 13.07.2016; in: "Proc. 2016 IEEE Computer Society Annual Symposium on VLSI", (2016), S. 490 - 495.

We present the first FPGA implementation of a
distributed clock synchronization algorithm with sub-nanosecond
skews that can tolerate arbitrary faults of individual components.
Each of n nodes is equipped with its own quartz oscillator and
the nodes broadcast their clock pulses to enable synchronization.
The algorithm provably maintains synchronization even if fewer
than n/3 nodes exhibit arbitrary faulty behavior. Moreover, as
long as more than 2n/3 nodes remain synchronized, nodes will
recover and resynchronize after transient faults.
Using 4 boards with Cyclone IV FPGAs, our implementation
achieves precision better than 300 ps. This is in accordance
with the worst-case precision of 870 ps predicted by theory.
Furthermore, our experiments demonstrate that nodes recover
from transient faults as described above. Finally, frequency
stability of the overall system improved by an order of magnitude.

Circuit faults, Synchronization, Algorithm design and analysis, Fault tolerance

http://dx.doi.org/10.1109/ISVLSI.2016.88