[Zurück]

B. Cilku, W. Puffitsch, D. Prokesch, M. Schoeberl, P. Puschner:
"Improving Performance of Single-path Code Through a Time-predictable Memory Hierarchy";
Vortrag: 20th IEEE International Symposium on Real-Time Computing (ISORC 2017), Toronto, Canada; 16.05.2017 - 18.05.2017; in: "Proc. 20th IEEE International Symposium on Real-Time Computing (ISORC 2017)", IEEE, (2017), ISBN: 978-1-5386-1574-4; S. 76 - 83.

Deriving the Worst-Case Execution Time (WCET) of a task is a challenging process, especially for processor architectures that use caches, out-of-order pipelines, and speculative execution. Despite existing contributions to WCET analysis for these complex architectures, there are open problems. The single-path code generation overcomes these problems by generating time-predictable code that has a single execution trace. However, the simplicity of this approach comes at the cost of longer execution times. This paper addresses performance improvements for single-path code. We propose a time-predictable memory hierarchy with a prefetcher that exploits the predictability of execution traces in single-path code to speed up code execution. The new memory hierarchy reduces both the cache-miss penalty time and the cache-miss rate on the instruction cache. The benefit of the approach is demonstrated through benchmarks that are executed on an FPGA implementation.

Time-predictable Memory Hierarchy, Single-path Code, Prefetching, Hardware, Process control, Real-time systems, Pipelines, Computer architecture

http://dx.doi.org/10.1109/ISORC.2017.17