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Talks and Poster Presentations (with Proceedings-Entry):

T. Polzer, F. Huemer, A. Steininger:
"Measuring Metastability Using a Time-to-Digital Converter";
Talk: 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Dresden; 2017-04-19 - 2017-04-21; in: "Proceedings 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", IEEE Service Center, (2017), ISBN: 978-1-5386-0471-7; Paper ID 55, 6 pages.



English abstract:
In view of the numerous clock domain crossings
found in modern systems-on-chip and multicore architectures
precise metastability characterization is a fundamental task. We
propose a conceptually novel approach for the experimental
assessment of upset rate over resolution time that is usually
employed to extract the relevant characteristics. Our method
is based on connecting a time-to-digital converter to the output
of the flip flop under test, rather than using a phase shifted
clock, as conventionally done. We present the details of an FPGA
implementation of our approach and show its feasibility through
an experimental evaluation, whose results favorably match those
obtained by the conventional method. The benefits of the novel
scheme are the ability to perform a calibration for the delay steps,
a speed-up of the measurement process, and the availability of
a more comprehensive and ordered measurement data set.

Keywords:
metastability, time-to-digital converter, TDC, late transition detection, carry chain


"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)
http://dx.doi.org/10.1109/DDECS.2017.7934582


Created from the Publication Database of the Vienna University of Technology.