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Talks and Poster Presentations (with Proceedings-Entry):

B. Prabakaran, S. Rehman, M. Hanif, S. Ullah, G. Mazaheri, A. Kumar, M. Shafique:
"DeMAS: An Efficient Design Methodology for Building Approximate Adders for FPGA-Based Systems";
Poster: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE'18), Dresden, Deutschland; 2018-03-19 - 2018-03-23; in: "IEEE/ACM 21st Design, Automation and Test in Europe Conference & Exhibition (DATE)", (2018), ISBN: 978-3-9819263-1-6; 917 - 920.



English abstract:
The current state-of-the-art approximate adders are mostly ASIC-based, i.e., they focus solely on gate and/or transistor level approximations (e.g., through circuit simplification or truncation) to achieve area, latency, power and/or energy savings at the cost of accuracy loss. However, when these designs are synthesized for FPGA-based systems, they do not offer similar reductions in area, latency and power/energy due to the underlying architectural differences between ASICs and FPGAs. In this paper, we present a novel generic design methodology to synthesize and implement approximate adders for any FPGA-based system by considering the underlying resources and architectural differences. Using our methodology, we have designed, analyzed and presented eight different multi-bit adder architectures. Compared to the 16-bit accurate adder, our designs are successful in achieving area, latency and power-delay product gains of 50%, 38%, and 53%, respectively. We also compare our approximate adders to state-of-the-art approximate adders specialized for ASIC and FPGA fabrics and demonstrate the benefits of our approach. We will make the RTL and behavioral models of our and state-of-the-art designs open-source at https://sourceforge.net/projects/approxfpgas/ to further fuel the research and development in the FPGA community and to ensure reproducible research.

Keywords:
Approximate Computing, FPGA, Adders, LUTs, Optimization, Design Flow, Efficiency, Area, Power, Performance, CAD


"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)
http://dx.doi.org/10.23919/DATE.2018.8342140


Created from the Publication Database of the Vienna University of Technology.