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S. Ullah, S. Rehman, B. Prabakaran, F. Kriebel, M. Hanif, M. Shafique, A. Kumar:
"Area-Optimized Low-Latency Approximate Multipliers for FPGA-based Hardware Accelerators";
Vortrag: 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), San Fransisco, USA; 24.06.2018 - 28.06.2018; in: "2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)", (2018), ISSN: 0738-100x; S. 1 - 6.

The architectural differences between ASICs and FPGAs limit the effective performance gains achievable by the application of ASIC-based approximation principles for FPGA-based reconfigurable computing systems. This paper presents a novel approximate multiplier architecture customized towards the FPGA-based fabrics, an efficient design methodology, and an open-source library. Our designs provide higher area, latency and energy gains along with better output accuracy than those offered by the state-of-the-art ASIC-based approximate multipliers. Moreover, compared to the multiplier IP offered by the Xilinx Vivado, our proposed design achieves up to 30%, 53%, and 67% gains in terms of area, latency, and energy, respectively, while incurring an insignificant accuracy loss (on average, below 1% average relative error). Our library of approximate multipliers is open-source and available online at https://cfaed.tudresden.de/pd-downloads to fuel further research and development in this area, and thereby enabling a new research direction for the FPGA community.

http://dx.doi.org/10.1109/DAC.2018.8465781