Publications in Scientific Journals:

J. Wang, M. Ebrahimi, L. Huang, X. Xie, Q. Li, G. Li, A. Jantsch:
"Efficient Design-for-Test Approach for Networks-on-Chip";
IEEE Transactions on Computers, 1 (2018), 1; 1 - 16.

English abstract:
To achieve high reliability in on-chip networks, it is necessary to test the network continuously with Built-in Self-Tests (BIST) so that the faults can be detected quickly and the number of affected packets can be minimized. However, BIST causes significant performance loss due to data dependencies. We propose EsyTest, a comprehensive test strategy with minimized influence on system performance. EsyTest tests the data path and the control path separately. The data path test starts periodically, but the actual test performs in the free time slots to avoid deactivating the router for testing. A reconfigurable router architecture and an adaptive fault-tolerant routing algorithm are proposed to guarantee the access to the processing core when the associated router is under test. During the whole test procedure of the network, all processing cores are accessible, and thus the system performance is maintained during the test. At the same time, EsyTest provides full test coverage of NoC and better hardware compatibility comparing with the existing test strategies. Under the PARSEC benchmark and different test frequencies, the execution time increases less than 5% at the cost of 9.9% more area and 4.6% more power in comparison with the execution where no test procedure is applied.

"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)

Electronic version of the publication:

Created from the Publication Database of the Vienna University of Technology.