Talks and Poster Presentations (with Proceedings-Entry):
N. Manjunath, D. Haerle, C. Manthey, M. Väänänen, S. Sabanal, H. Eichinger, H. Tauber, A. Machne, R. Grosu, D. Nickovic:
"Production Tests Coverage Analysis in the Simulation Environment";
Talk: International Test Conference,
Phoenix, Arizona, USA;
- 2018-11-02; in: "ITC'18, the International Test Conference",
2018 IEEE International Test Conference (ITC)
In the semiconductor industry, field returns have a negative impact with large costs and potential loss of reputation. As a consequence, a good coverage of the production tests with respect to the common manufacturing defects is essential to ensure the quality of the product to be delivered. Defect simulation is imperative to obtain coverage, however long simulation duration of the production tests can be a huge obstacle. Hence, there is an emergent need for novel methodologies to obtain coverage analysis of AMS chip production tests. In this paper, we address several aspects that are necessary to develop such a methodology. We first propose a method to identify a fault model that mimics the common manufacturing defects and extract all such faults from the DUT layout, we then develop a test ordering procedure that for a given fault selects the test from an existing test suite that is the most likely to detect the fault. The test ordering technique allows to avoid the execution of many tests during the coverage analysis and thus save considerable amounts of simulation time. We demonstrate the applicability and efficiency of the resulting techniques on an AMS design from Infineon Technologies AG.
"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)
Created from the Publication Database of the Vienna University of Technology.